/***************************************************************************
 *                      COPYRIGHT NOTICE
 *             Copyright 2019 Horizon Robotics, Inc.
 *                     All rights reserved.
 ***************************************************************************/

#ifndef __HOBOT_PYM_REG_H__
#define __HOBOT_PYM_REG_H__


#include "vio_hw_common_api.h"
#include "hobot_dev_pym.h"


enum pym_shadow_id{
	SDW_ID_0,
	SDW_ID_1,
	SDW_ID_2,
	SDW_ID_3,
	SDW_ID_END,
};

enum pym_reg {
	PYM_PYRAMID_CTRL,
	PYM_IMG_Y_ADDR_DDR,
	PYM_IMG_C_ADDR_DDR,
	PYM_IMG_ADDR_Y,
	PYM_IMG_Y_ADDR_DDR_P1,
	PYM_IMG_Y_ADDR_DDR_P2,
	PYM_IMG_Y_ADDR_DDR_P3,
	PYM_IMG_Y_ADDR_DDR_P4,
	PYM_IMG_Y_ADDR_DDR_P5,
	PYM_IMG_Y_ADDR_DDR_P6,
	PYM_IMG_Y_ADDR_DDR_P7,
	PYM_IMG_Y_ADDR_DDR_P8,
	PYM_IMG_Y_ADDR_DDR_P9,
	PYM_IMG_Y_ADDR_DDR_P10,
	PYM_IMG_Y_ADDR_DDR_P11,
	PYM_IMG_Y_ADDR_DDR_P12,
	PYM_IMG_Y_ADDR_DDR_P13,
	PYM_IMG_Y_ADDR_DDR_P14,
	PYM_IMG_Y_ADDR_DDR_P15,
	PYM_IMG_Y_ADDR_DDR_P16,
	PYM_IMG_Y_ADDR_DDR_P17,
	PYM_IMG_Y_ADDR_DDR_P18,
	PYM_IMG_Y_ADDR_DDR_P19,
	PYM_IMG_Y_ADDR_DDR_P20,
	PYM_IMG_Y_ADDR_DDR_P21,
	PYM_IMG_Y_ADDR_DDR_P22,
	PYM_IMG_Y_ADDR_DDR_P23,
	PYM_IMG_ADDR_C,
	PYM_IMG_C_ADDR_DDR_P1,
	PYM_IMG_C_ADDR_DDR_P2,
	PYM_IMG_C_ADDR_DDR_P3,
	PYM_IMG_C_ADDR_DDR_P4,
	PYM_IMG_C_ADDR_DDR_P5,
	PYM_IMG_C_ADDR_DDR_P6,
	PYM_IMG_C_ADDR_DDR_P7,
	PYM_IMG_C_ADDR_DDR_P8,
	PYM_IMG_C_ADDR_DDR_P9,
	PYM_IMG_C_ADDR_DDR_P10,
	PYM_IMG_C_ADDR_DDR_P11,
	PYM_IMG_C_ADDR_DDR_P12,
	PYM_IMG_C_ADDR_DDR_P13,
	PYM_IMG_C_ADDR_DDR_P14,
	PYM_IMG_C_ADDR_DDR_P15,
	PYM_IMG_C_ADDR_DDR_P16,
	PYM_IMG_C_ADDR_DDR_P17,
	PYM_IMG_C_ADDR_DDR_P18,
	PYM_IMG_C_ADDR_DDR_P19,
	PYM_IMG_C_ADDR_DDR_P20,
	PYM_IMG_C_ADDR_DDR_P21,
	PYM_IMG_C_ADDR_DDR_P22,
	PYM_IMG_C_ADDR_DDR_P23,
	PYM_IMG_Y_ADDR_U0,
	PYM_IMG_Y_ADDR_U1,
	PYM_IMG_Y_ADDR_U2,
	PYM_IMG_Y_ADDR_U3,
	PYM_IMG_Y_ADDR_U4,
	PYM_IMG_Y_ADDR_U5,
	PYM_IMG_C_ADDR_U0,
	PYM_IMG_C_ADDR_U1,
	PYM_IMG_C_ADDR_U2,
	PYM_IMG_C_ADDR_U3,
	PYM_IMG_C_ADDR_U4,
	PYM_IMG_C_ADDR_U5,
	PYM_ERR_CNT,
	PYM_CFG,
	PYM_CTRL_WM_0,
	PYM_CTRL_WM_1,
	PYM_CTRL_WM_2,
	PYM_CTRL_WM_3,
	PYM_CTRL_WM_4,
	PYM_CTRL_WM_5,
	PYM_CTRL_RM_0,
	PYM_CTRL_RM_1,
	PYM_WR_LINE,
	PYM_FRAME_ID,
	PYM_INT_MASK,
	PYM_INT_STATUS,
	PYM_DDR_START,
	PYM_FRAME_ID_VALUE,
	PYM_CONFIG_ID,
	PYM_CONFIG_RDY,

	PYM_0_PYRAMIDE_DS_CTRL,
	PYM_0_PYRAMIDE_US_CTRL,
	PYM_0_IMG_RES_SRC,
	PYM_0_DS_FACTOR_1,
	PYM_0_DS_FACTOR_2,
	PYM_0_DS_FACTOR_3,
	PYM_0_DS_FACTOR_4,
	PYM_0_ROI0_P1,
	PYM_0_ROI1_P1,
	PYM_0_ROI0_P2,
	PYM_0_ROI1_P2,
	PYM_0_ROI0_P3,
	PYM_0_ROI1_P3,
	PYM_0_ROI0_P5,
	PYM_0_ROI1_P5,
	PYM_0_ROI0_P6,
	PYM_0_ROI1_P6,
	PYM_0_ROI0_P7,
	PYM_0_ROI1_P7,
	PYM_0_ROI0_P9,
	PYM_0_ROI1_P9,
	PYM_0_ROI0_P10,
	PYM_0_ROI1_P10,
	PYM_0_ROI0_P11,
	PYM_0_ROI1_P11,
	PYM_0_ROI0_P13,
	PYM_0_ROI1_P13,
	PYM_0_ROI0_P14,
	PYM_0_ROI1_P14,
	PYM_0_ROI0_P15,
	PYM_0_ROI1_P15,
	PYM_0_ROI0_P17,
	PYM_0_ROI1_P17,
	PYM_0_ROI0_P18,
	PYM_0_ROI1_P18,
	PYM_0_ROI0_P19,
	PYM_0_ROI1_P19,
	PYM_0_ROI0_P21,
	PYM_0_ROI1_P21,
	PYM_0_ROI0_P22,
	PYM_0_ROI1_P22,
	PYM_0_ROI0_P23,
	PYM_0_ROI1_P23,
	PYM_0_ROI0_U0,
	PYM_0_ROI1_U0,
	PYM_0_ROI0_U1,
	PYM_0_ROI1_U1,
	PYM_0_ROI0_U2,
	PYM_0_ROI1_U2,
	PYM_0_ROI0_U3,
	PYM_0_ROI1_U3,
	PYM_0_ROI0_U4,
	PYM_0_ROI1_U4,
	PYM_0_ROI0_U5,
	PYM_0_ROI1_U5,
	PYM_0_US_FACTOR_1,
	PYM_0_US_FACTOR_2,
	PYM_0_SRC_WIDTH_DS1,
	PYM_0_SRC_WIDTH_DS2,
	PYM_0_SRC_WIDTH_DS3,
	PYM_0_SRC_WIDTH_DS4,
	PYM_0_SRC_WIDTH_DS5,
	PYM_0_SRC_WIDTH_DS6,
	PYM_0_SRC_WIDTH_DS7,
	PYM_0_SRC_WIDTH_DS8,
	PYM_0_SRC_WIDTH_DS9,
	PYM_0_SRC_WIDTH_US1,
	PYM_0_SRC_WIDTH_US2,
	PYM_0_SRC_WIDTH_US3,
	PYM_0_CONFIG_RDY,

	PYM_1_PYRAMIDE_DS_CTRL,
	PYM_1_PYRAMIDE_US_CTRL,
	PYM_1_IMG_RES_SRC,
	PYM_1_DS_FACTOR_1,
	PYM_1_DS_FACTOR_2,
	PYM_1_DS_FACTOR_3,
	PYM_1_DS_FACTOR_4,
	PYM_1_ROI0_P1,
	PYM_1_ROI1_P1,
	PYM_1_ROI0_P2,
	PYM_1_ROI1_P2,
	PYM_1_ROI0_P3,
	PYM_1_ROI1_P3,
	PYM_1_ROI0_P5,
	PYM_1_ROI1_P5,
	PYM_1_ROI0_P6,
	PYM_1_ROI1_P6,
	PYM_1_ROI0_P7,
	PYM_1_ROI1_P7,
	PYM_1_ROI0_P9,
	PYM_1_ROI1_P9,
	PYM_1_ROI0_P10,
	PYM_1_ROI1_P10,
	PYM_1_ROI0_P11,
	PYM_1_ROI1_P11,
	PYM_1_ROI0_P13,
	PYM_1_ROI1_P13,
	PYM_1_ROI0_P14,
	PYM_1_ROI1_P14,
	PYM_1_ROI0_P15,
	PYM_1_ROI1_P15,
	PYM_1_ROI0_P17,
	PYM_1_ROI1_P17,
	PYM_1_ROI0_P18,
	PYM_1_ROI1_P18,
	PYM_1_ROI0_P19,
	PYM_1_ROI1_P19,
	PYM_1_ROI0_P21,
	PYM_1_ROI1_P21,
	PYM_1_ROI0_P22,
	PYM_1_ROI1_P22,
	PYM_1_ROI0_P23,
	PYM_1_ROI1_P23,
	PYM_1_ROI0_U0,
	PYM_1_ROI1_U0,
	PYM_1_ROI0_U1,
	PYM_1_ROI1_U1,
	PYM_1_ROI0_U2,
	PYM_1_ROI1_U2,
	PYM_1_ROI0_U3,
	PYM_1_ROI1_U3,
	PYM_1_ROI0_U4,
	PYM_1_ROI1_U4,
	PYM_1_ROI0_U5,
	PYM_1_ROI1_U5,
	PYM_1_US_FACTOR_1,
	PYM_1_US_FACTOR_2,
	PYM_1_SRC_WIDTH_DS1,
	PYM_1_SRC_WIDTH_DS2,
	PYM_1_SRC_WIDTH_DS3,
	PYM_1_SRC_WIDTH_DS4,
	PYM_1_SRC_WIDTH_DS5,
	PYM_1_SRC_WIDTH_DS6,
	PYM_1_SRC_WIDTH_DS7,
	PYM_1_SRC_WIDTH_DS8,
	PYM_1_SRC_WIDTH_DS9,
	PYM_1_SRC_WIDTH_US1,
	PYM_1_SRC_WIDTH_US2,
	PYM_1_SRC_WIDTH_US3,
	PYM_1_CONFIG_RDY,
	
	PYM_2_PYRAMIDE_DS_CTRL,
	PYM_2_PYRAMIDE_US_CTRL,
	PYM_2_IMG_RES_SRC,
	PYM_2_DS_FACTOR_1,
	PYM_2_DS_FACTOR_2,
	PYM_2_DS_FACTOR_3,
	PYM_2_DS_FACTOR_4,
	PYM_2_ROI0_P1,
	PYM_2_ROI1_P1,
	PYM_2_ROI0_P2,
	PYM_2_ROI1_P2,
	PYM_2_ROI0_P3,
	PYM_2_ROI1_P3,
	PYM_2_ROI0_P5,
	PYM_2_ROI1_P5,
	PYM_2_ROI0_P6,
	PYM_2_ROI1_P6,
	PYM_2_ROI0_P7,
	PYM_2_ROI1_P7,
	PYM_2_ROI0_P9,
	PYM_2_ROI1_P9,
	PYM_2_ROI0_P10,
	PYM_2_ROI1_P10,
	PYM_2_ROI0_P11,
	PYM_2_ROI1_P11,
	PYM_2_ROI0_P13,
	PYM_2_ROI1_P13,
	PYM_2_ROI0_P14,
	PYM_2_ROI1_P14,
	PYM_2_ROI0_P15,
	PYM_2_ROI1_P15,
	PYM_2_ROI0_P17,
	PYM_2_ROI1_P17,
	PYM_2_ROI0_P18,
	PYM_2_ROI1_P18,
	PYM_2_ROI0_P19,
	PYM_2_ROI1_P19,
	PYM_2_ROI0_P21,
	PYM_2_ROI1_P21,
	PYM_2_ROI0_P22,
	PYM_2_ROI1_P22,
	PYM_2_ROI0_P23,
	PYM_2_ROI1_P23,
	PYM_2_ROI0_U0,
	PYM_2_ROI1_U0,
	PYM_2_ROI0_U1,
	PYM_2_ROI1_U1,
	PYM_2_ROI0_U2,
	PYM_2_ROI1_U2,
	PYM_2_ROI0_U3,
	PYM_2_ROI1_U3,
	PYM_2_ROI0_U4,
	PYM_2_ROI1_U4,
	PYM_2_ROI0_U5,
	PYM_2_ROI1_U5,
	PYM_2_US_FACTOR_1,
	PYM_2_US_FACTOR_2,
	PYM_2_SRC_WIDTH_DS1,
	PYM_2_SRC_WIDTH_DS2,
	PYM_2_SRC_WIDTH_DS3,
	PYM_2_SRC_WIDTH_DS4,
	PYM_2_SRC_WIDTH_DS5,
	PYM_2_SRC_WIDTH_DS6,
	PYM_2_SRC_WIDTH_DS7,
	PYM_2_SRC_WIDTH_DS8,
	PYM_2_SRC_WIDTH_DS9,
	PYM_2_SRC_WIDTH_US1,
	PYM_2_SRC_WIDTH_US2,
	PYM_2_SRC_WIDTH_US3,
	PYM_2_CONFIG_RDY,

	PYM_3_PYRAMIDE_DS_CTRL,
	PYM_3_PYRAMIDE_US_CTRL,
	PYM_3_IMG_RES_SRC,
	PYM_3_DS_FACTOR_1,
	PYM_3_DS_FACTOR_2,
	PYM_3_DS_FACTOR_3,
	PYM_3_DS_FACTOR_4,
	PYM_3_ROI0_P1,
	PYM_3_ROI1_P1,
	PYM_3_ROI0_P2,
	PYM_3_ROI1_P2,
	PYM_3_ROI0_P3,
	PYM_3_ROI1_P3,
	PYM_3_ROI0_P5,
	PYM_3_ROI1_P5,
	PYM_3_ROI0_P6,
	PYM_3_ROI1_P6,
	PYM_3_ROI0_P7,
	PYM_3_ROI1_P7,
	PYM_3_ROI0_P9,
	PYM_3_ROI1_P9,
	PYM_3_ROI0_P10,
	PYM_3_ROI1_P10,
	PYM_3_ROI0_P11,
	PYM_3_ROI1_P11,
	PYM_3_ROI0_P13,
	PYM_3_ROI1_P13,
	PYM_3_ROI0_P14,
	PYM_3_ROI1_P14,
	PYM_3_ROI0_P15,
	PYM_3_ROI1_P15,
	PYM_3_ROI0_P17,
	PYM_3_ROI1_P17,
	PYM_3_ROI0_P18,
	PYM_3_ROI1_P18,
	PYM_3_ROI0_P19,
	PYM_3_ROI1_P19,
	PYM_3_ROI0_P21,
	PYM_3_ROI1_P21,
	PYM_3_ROI0_P22,
	PYM_3_ROI1_P22,
	PYM_3_ROI0_P23,
	PYM_3_ROI1_P23,
	PYM_3_ROI0_U0,
	PYM_3_ROI1_U0,
	PYM_3_ROI0_U1,
	PYM_3_ROI1_U1,
	PYM_3_ROI0_U2,
	PYM_3_ROI1_U2,
	PYM_3_ROI0_U3,
	PYM_3_ROI1_U3,
	PYM_3_ROI0_U4,
	PYM_3_ROI1_U4,
	PYM_3_ROI0_U5,
	PYM_3_ROI1_U5,
	PYM_3_US_FACTOR_1,
	PYM_3_US_FACTOR_2,
	PYM_3_SRC_WIDTH_DS1,
	PYM_3_SRC_WIDTH_DS2,
	PYM_3_SRC_WIDTH_DS3,
	PYM_3_SRC_WIDTH_DS4,
	PYM_3_SRC_WIDTH_DS5,
	PYM_3_SRC_WIDTH_DS6,
	PYM_3_SRC_WIDTH_DS7,
	PYM_3_SRC_WIDTH_DS8,
	PYM_3_SRC_WIDTH_DS9,
	PYM_3_SRC_WIDTH_US1,
	PYM_3_SRC_WIDTH_US2,
	PYM_3_SRC_WIDTH_US3,
	PYM_3_CONFIG_RDY,
	NUM_OF_PYM_REG,
};

static struct vio_reg_def pym_regs[NUM_OF_PYM_REG]={
	{"PYM_PYRAMID_CTRL",       0x0000, RW},
	{"PYM_IMG_Y_ADDR_DDR",     0x0004, RW},
	{"PYM_IMG_C_ADDR_DDR",     0x0008, RW},
	{"PYM_IMG_ADDR_Y",         0x000c, RW},
	{"PYM_IMG_Y_ADDR_DDR_P1",  0x0010, RW},
	{"PYM_IMG_Y_ADDR_DDR_P2",  0x0014, RW},
	{"PYM_IMG_Y_ADDR_DDR_P3",  0x0018, RW},
	{"PYM_IMG_Y_ADDR_DDR_P4",  0x001c, RW},
	{"PYM_IMG_Y_ADDR_DDR_P5",  0x0020, RW},
	{"PYM_IMG_Y_ADDR_DDR_P6",  0x0024, RW},
	{"PYM_IMG_Y_ADDR_DDR_P7",  0x0028, RW},
	{"PYM_IMG_Y_ADDR_DDR_P8",  0x002c, RW},
	{"PYM_IMG_Y_ADDR_DDR_P9",  0x0030, RW},
	{"PYM_IMG_Y_ADDR_DDR_P10", 0x0034, RW},
	{"PYM_IMG_Y_ADDR_DDR_P11", 0x0038, RW},
	{"PYM_IMG_Y_ADDR_DDR_P12", 0x003c, RW},
	{"PYM_IMG_Y_ADDR_DDR_P13", 0x0040, RW},
	{"PYM_IMG_Y_ADDR_DDR_P14", 0x0044, RW},
	{"PYM_IMG_Y_ADDR_DDR_P15", 0x0048, RW},
	{"PYM_IMG_Y_ADDR_DDR_P16", 0x004c, RW},
	{"PYM_IMG_Y_ADDR_DDR_P17", 0x0050, RW},
	{"PYM_IMG_Y_ADDR_DDR_P18", 0x0054, RW},
	{"PYM_IMG_Y_ADDR_DDR_P19", 0x0058, RW},
	{"PYM_IMG_Y_ADDR_DDR_P20", 0x005c, RW},
	{"PYM_IMG_Y_ADDR_DDR_P21", 0x0060, RW},
	{"PYM_IMG_Y_ADDR_DDR_P22", 0x0064, RW},
	{"PYM_IMG_Y_ADDR_DDR_P23", 0x0068, RW},
	{"PYM_IMG_ADDR_C",         0x006c, RW},
	{"PYM_IMG_C_ADDR_DDR_P1",  0x0070, RW},
	{"PYM_IMG_C_ADDR_DDR_P2",  0x0074, RW},
	{"PYM_IMG_C_ADDR_DDR_P3",  0x0078, RW},
	{"PYM_IMG_C_ADDR_DDR_P4",  0x007c, RW},
	{"PYM_IMG_C_ADDR_DDR_P5",  0x0080, RW},
	{"PYM_IMG_C_ADDR_DDR_P6",  0x0084, RW},
	{"PYM_IMG_C_ADDR_DDR_P7",  0x0088, RW},
	{"PYM_IMG_C_ADDR_DDR_P8",  0x008c, RW},
	{"PYM_IMG_C_ADDR_DDR_P9",  0x0090, RW},
	{"PYM_IMG_C_ADDR_DDR_P10", 0x0094, RW},
	{"PYM_IMG_C_ADDR_DDR_P11", 0x0098, RW},
	{"PYM_IMG_C_ADDR_DDR_P12", 0x009c, RW},
	{"PYM_IMG_C_ADDR_DDR_P13", 0x00a0, RW},
	{"PYM_IMG_C_ADDR_DDR_P14", 0x00a4, RW},
	{"PYM_IMG_C_ADDR_DDR_P15", 0x00a8, RW},
	{"PYM_IMG_C_ADDR_DDR_P16", 0x00ac, RW},
	{"PYM_IMG_C_ADDR_DDR_P17", 0x00b0, RW},
	{"PYM_IMG_C_ADDR_DDR_P18", 0x00b4, RW},
	{"PYM_IMG_C_ADDR_DDR_P19", 0x00b8, RW},
	{"PYM_IMG_C_ADDR_DDR_P20", 0x00bc, RW},
	{"PYM_IMG_C_ADDR_DDR_P21", 0x00c0, RW},
	{"PYM_IMG_C_ADDR_DDR_P22", 0x00c4, RW},
	{"PYM_IMG_C_ADDR_DDR_P23", 0x00c8, RW},
	{"PYM_IMG_Y_ADDR_U0",      0x00cc, RW},
	{"PYM_IMG_Y_ADDR_U1",      0x00d0, RW},
	{"PYM_IMG_Y_ADDR_U2",      0x00d4, RW},
	{"PYM_IMG_Y_ADDR_U3",      0x00d8, RW},
	{"PYM_IMG_Y_ADDR_U4",      0x00dc, RW},
	{"PYM_IMG_Y_ADDR_U5",      0x00e0, RW},
	{"PYM_IMG_C_ADDR_U0",      0x00e4, RW},
	{"PYM_IMG_C_ADDR_U1",      0x00e8, RW},
	{"PYM_IMG_C_ADDR_U2",      0x00ec, RW},
	{"PYM_IMG_C_ADDR_U3",      0x00f0, RW},
	{"PYM_IMG_C_ADDR_U4",      0x00f4, RW},
	{"PYM_IMG_C_ADDR_U5",      0x00f8, RW},
	{"PYM_ERR_CNT",            0x00fc, RAC},
	{"PYM_CFG",         	   0x0100, RW},
	{"PYM_CTRL_WM_0",          0x0104, RW},
	{"PYM_CTRL_WM_1",          0x0108, RW},
	{"PYM_CTRL_WM_2",          0x010c, RW},
	{"PYM_CTRL_WM_3",          0x0100, RW},
	{"PYM_CTRL_WM_4",          0x0114, RW},
	{"PYM_CTRL_WM_5",          0x0118, RW},
	{"PYM_CTRL_RM_0",          0x011c, RW},
	{"PYM_CTRL_RM_1",          0x0110, RW},
	{"PYM_WR_LINE",            0x0124, RW},
	{"PYM_FRAME_ID",           0x0128, RW},
	{"PYM_INT_MASK",           0x012c, RW},
	{"PYM_INT_STATUS",         0x0130, W1C},
	{"PYM_DDR_START",          0x0134, WO},
	{"PYM_FRAME_ID_VALUE",     0x0138, RO},
	{"PYM_CONFIG_ID",          0x013c, RW},
	{"PYM_CONFIG_RDY",         0x0140, RW},

	{"PYM_0_PYRAMIDE_DS_CTRL", 0x0200, RW},
	{"PYM_0_PYRAMIDE_US_CTRL", 0x0204, RW},
	{"PYM_0_IMG_RES_SRC",      0x0208, RW},
	{"PYM_0_DS_FACTOR_1",      0x020c, RW},
	{"PYM_0_DS_FACTOR_2",      0x0210, RW},
	{"PYM_0_DS_FACTOR_3",      0x0214, RW},
	{"PYM_0_DS_FACTOR_4",      0x0218, RW},
	{"PYM_0_ROI0_P1",          0x021c, RW},
	{"PYM_0_ROI1_P1",          0x0220, RW},
	{"PYM_0_ROI0_P2",          0x0224, RW},
	{"PYM_0_ROI1_P2",          0x0228, RW},
	{"PYM_0_ROI0_P3",          0x022c, RW},
	{"PYM_0_ROI1_P3",          0x0230, RW},
	{"PYM_0_ROI0_P5",          0x0234, RW},
	{"PYM_0_ROI1_P5",          0x0238, RW},
	{"PYM_0_ROI0_P6",          0x023c, RW},
	{"PYM_0_ROI1_P6",          0x0240, RW},
	{"PYM_0_ROI0_P7",          0x0244, RW},
	{"PYM_0_ROI1_P7",          0x0248, RW},
	{"PYM_0_ROI0_P9",          0x024c, RW},
	{"PYM_0_ROI1_P9",          0x0250, RW},
	{"PYM_0_ROI0_P10",         0x0254, RW},
	{"PYM_0_ROI1_P10",         0x0258, RW},
	{"PYM_0_ROI0_P11",         0x025c, RW},
	{"PYM_0_ROI1_P11",         0x0260, RW},
	{"PYM_0_ROI0_P13",         0x0264, RW},
	{"PYM_0_ROI1_P13",         0x0268, RW},
	{"PYM_0_ROI0_P14",         0x026c, RW},
	{"PYM_0_ROI1_P14",         0x0270, RW},
	{"PYM_0_ROI0_P15",         0x0274, RW},
	{"PYM_0_ROI1_P15",         0x0278, RW},
	{"PYM_0_ROI0_P17",         0x027c, RW},
	{"PYM_0_ROI1_P17",         0x0280, RW},
	{"PYM_0_ROI0_P18",         0x0284, RW},
	{"PYM_0_ROI1_P18",         0x0288, RW},
	{"PYM_0_ROI0_P19",         0x028c, RW},
	{"PYM_0_ROI1_P19",         0x0290, RW},
	{"PYM_0_ROI0_P21",         0x0294, RW},
	{"PYM_0_ROI1_P21",         0x0298, RW},
	{"PYM_0_ROI0_P22",         0x029c, RW},
	{"PYM_0_ROI1_P22",         0x02a0, RW},
	{"PYM_0_ROI0_P23",         0x02a4, RW},
	{"PYM_0_ROI1_P23",         0x02a8, RW},
	{"PYM_0_ROI0_U0",          0x02ac, RW},
	{"PYM_0_ROI1_U0",          0x02b0, RW},
	{"PYM_0_ROI0_U1",          0x02b4, RW},
	{"PYM_0_ROI1_U1",          0x02b8, RW},
	{"PYM_0_ROI0_U2",          0x02bc, RW},
	{"PYM_0_ROI1_U2",          0x02c0, RW},
	{"PYM_0_ROI0_U3",          0x02c4, RW},
	{"PYM_0_ROI1_U3",          0x02c8, RW},
	{"PYM_0_ROI0_U4",          0x02cc, RW},
	{"PYM_0_ROI1_U4",          0x02d0, RW},
	{"PYM_0_ROI0_U5",          0x02d4, RW},
	{"PYM_0_ROI1_U5",          0x02d8, RW},
	{"PYM_0_US_FACTOR_1",      0x02dc, RW},
	{"PYM_0_US_FACTOR_2",      0x02e0, RW},
	{"PYM_0_SRC_WIDTH_DS1",    0x02e4, RW},
	{"PYM_0_SRC_WIDTH_DS2",    0x02e8, RW},
	{"PYM_0_SRC_WIDTH_DS3",    0x02ec, RW},
	{"PYM_0_SRC_WIDTH_DS4",    0x02f0, RW},
	{"PYM_0_SRC_WIDTH_DS5",    0x02f4, RW},
	{"PYM_0_SRC_WIDTH_DS6",    0x02f8, RW},
	{"PYM_0_SRC_WIDTH_DS7",    0x02fc, RW},
	{"PYM_0_SRC_WIDTH_DS8",    0x0300, RW},
	{"PYM_0_SRC_WIDTH_DS9",    0x0304, RW},
	{"PYM_0_SRC_WIDTH_US1",    0x0308, RW},
	{"PYM_0_SRC_WIDTH_US2",    0x030c, RW},
	{"PYM_0_SRC_WIDTH_US3",    0x0310, RW},
	{"PYM_0_CONFIG_RDY",       0x0314, RW},

	{"PYM_1_PYRAMIDE_DS_CTRL", 0x0400, RW},
	{"PYM_1_PYRAMIDE_US_CTRL", 0x0404, RW},
	{"PYM_1_IMG_RES_SRC",      0x0408, RW},
	{"PYM_1_DS_FACTOR_1",      0x040c, RW},
	{"PYM_1_DS_FACTOR_2",      0x0410, RW},
	{"PYM_1_DS_FACTOR_3",      0x0414, RW},
	{"PYM_1_DS_FACTOR_4",      0x0418, RW},
	{"PYM_1_ROI0_P1",          0x041c, RW},
	{"PYM_1_ROI1_P1",          0x0420, RW},
	{"PYM_1_ROI0_P2",          0x0424, RW},
	{"PYM_1_ROI1_P2",          0x0428, RW},
	{"PYM_1_ROI0_P3",          0x042c, RW},
	{"PYM_1_ROI1_P3",          0x0430, RW},
	{"PYM_1_ROI0_P5",          0x0434, RW},
	{"PYM_1_ROI1_P5",          0x0438, RW},
	{"PYM_1_ROI0_P6",          0x043c, RW},
	{"PYM_1_ROI1_P6",          0x0440, RW},
	{"PYM_1_ROI0_P7",          0x0444, RW},
	{"PYM_1_ROI1_P7",          0x0448, RW},
	{"PYM_1_ROI0_P9",          0x044c, RW},
	{"PYM_1_ROI1_P9",          0x0450, RW},
	{"PYM_1_ROI0_P10",         0x0454, RW},
	{"PYM_1_ROI1_P10",         0x0458, RW},
	{"PYM_1_ROI0_P11",         0x045c, RW},
	{"PYM_1_ROI1_P11",         0x0460, RW},
	{"PYM_1_ROI0_P13",         0x0464, RW},
	{"PYM_1_ROI1_P13",         0x0468, RW},
	{"PYM_1_ROI0_P14",         0x046c, RW},
	{"PYM_1_ROI1_P14",         0x0470, RW},
	{"PYM_1_ROI0_P15",         0x0474, RW},
	{"PYM_1_ROI1_P15",         0x0478, RW},
	{"PYM_1_ROI0_P17",         0x047c, RW},
	{"PYM_1_ROI1_P17",         0x0480, RW},
	{"PYM_1_ROI0_P18",         0x0484, RW},
	{"PYM_1_ROI1_P18",         0x0488, RW},
	{"PYM_1_ROI0_P19",         0x048c, RW},
	{"PYM_1_ROI1_P19",         0x0490, RW},
	{"PYM_1_ROI0_P21",         0x0494, RW},
	{"PYM_1_ROI1_P21",         0x0498, RW},
	{"PYM_1_ROI0_P22",         0x049c, RW},
	{"PYM_1_ROI1_P22",         0x04a0, RW},
	{"PYM_1_ROI0_P23",         0x04a4, RW},
	{"PYM_1_ROI1_P23",         0x04a8, RW},
	{"PYM_1_ROI0_U0",          0x04ac, RW},
	{"PYM_1_ROI1_U0",          0x04b0, RW},
	{"PYM_1_ROI0_U1",          0x04b4, RW},
	{"PYM_1_ROI1_U1",          0x04b8, RW},
	{"PYM_1_ROI0_U2",          0x04bc, RW},
	{"PYM_1_ROI1_U2",          0x04c0, RW},
	{"PYM_1_ROI0_U3",          0x04c4, RW},
	{"PYM_1_ROI1_U3",          0x04c8, RW},
	{"PYM_1_ROI0_U4",          0x04cc, RW},
	{"PYM_1_ROI1_U4",          0x04d0, RW},
	{"PYM_1_ROI0_U5",          0x04d4, RW},
	{"PYM_1_ROI1_U5",          0x04d8, RW},
	{"PYM_1_US_FACTOR_1",      0x04dc, RW},
	{"PYM_1_US_FACTOR_2",      0x04e0, RW},
	{"PYM_1_SRC_WIDTH_DS1",    0x04e4, RW},
	{"PYM_1_SRC_WIDTH_DS2",    0x04e8, RW},
	{"PYM_1_SRC_WIDTH_DS3",    0x04ec, RW},
	{"PYM_1_SRC_WIDTH_DS4",    0x04f0, RW},
	{"PYM_1_SRC_WIDTH_DS5",    0x04f4, RW},
	{"PYM_1_SRC_WIDTH_DS6",    0x04f8, RW},
	{"PYM_1_SRC_WIDTH_DS7",    0x04fc, RW},
	{"PYM_1_SRC_WIDTH_DS8",    0x0500, RW},
	{"PYM_1_SRC_WIDTH_DS9",    0x0504, RW},
	{"PYM_1_SRC_WIDTH_US1",    0x0508, RW},
	{"PYM_1_SRC_WIDTH_US2",    0x050c, RW},
	{"PYM_1_SRC_WIDTH_US3",    0x0510, RW},
	{"PYM_1_CONFIG_RDY",       0x0514, RW},

	{"PYM_2_PYRAMIDE_DS_CTRL", 0x0600, RW},
	{"PYM_2_PYRAMIDE_US_CTRL", 0x0604, RW},
	{"PYM_2_IMG_RES_SRC",      0x0608, RW},
	{"PYM_2_DS_FACTOR_1",      0x060c, RW},
	{"PYM_2_DS_FACTOR_2",      0x0610, RW},
	{"PYM_2_DS_FACTOR_3",      0x0614, RW},
	{"PYM_2_DS_FACTOR_4",      0x0618, RW},
	{"PYM_2_ROI0_P1",          0x061c, RW},
	{"PYM_2_ROI1_P1",          0x0620, RW},
	{"PYM_2_ROI0_P2",          0x0624, RW},
	{"PYM_2_ROI1_P2",          0x0628, RW},
	{"PYM_2_ROI0_P3",          0x062c, RW},
	{"PYM_2_ROI1_P3",          0x0630, RW},
	{"PYM_2_ROI0_P5",          0x0634, RW},
	{"PYM_2_ROI1_P5",          0x0638, RW},
	{"PYM_2_ROI0_P6",          0x063c, RW},
	{"PYM_2_ROI1_P6",          0x0640, RW},
	{"PYM_2_ROI0_P7",          0x0644, RW},
	{"PYM_2_ROI1_P7",          0x0648, RW},
	{"PYM_2_ROI0_P9",          0x064c, RW},
	{"PYM_2_ROI1_P9",          0x0650, RW},
	{"PYM_2_ROI0_P10",         0x0654, RW},
	{"PYM_2_ROI1_P10",         0x0658, RW},
	{"PYM_2_ROI0_P11",         0x065c, RW},
	{"PYM_2_ROI1_P11",         0x0660, RW},
	{"PYM_2_ROI0_P13",         0x0664, RW},
	{"PYM_2_ROI1_P13",         0x0668, RW},
	{"PYM_2_ROI0_P14",         0x066c, RW},
	{"PYM_2_ROI1_P14",         0x0670, RW},
	{"PYM_2_ROI0_P15",         0x0674, RW},
	{"PYM_2_ROI1_P15",         0x0678, RW},
	{"PYM_2_ROI0_P17",         0x067c, RW},
	{"PYM_2_ROI1_P17",         0x0680, RW},
	{"PYM_2_ROI0_P18",         0x0684, RW},
	{"PYM_2_ROI1_P18",         0x0688, RW},
	{"PYM_2_ROI0_P19",         0x068c, RW},
	{"PYM_2_ROI1_P19",         0x0690, RW},
	{"PYM_2_ROI0_P21",         0x0694, RW},
	{"PYM_2_ROI1_P21",         0x0698, RW},
	{"PYM_2_ROI0_P22",         0x069c, RW},
	{"PYM_2_ROI1_P22",         0x06a0, RW},
	{"PYM_2_ROI0_P23",         0x06a4, RW},
	{"PYM_2_ROI1_P23",         0x06a8, RW},
	{"PYM_2_ROI0_U0",          0x06ac, RW},
	{"PYM_2_ROI1_U0",          0x06b0, RW},
	{"PYM_2_ROI0_U1",          0x06b4, RW},
	{"PYM_2_ROI1_U1",          0x06b8, RW},
	{"PYM_2_ROI0_U2",          0x06bc, RW},
	{"PYM_2_ROI1_U2",          0x06c0, RW},
	{"PYM_2_ROI0_U3",          0x06c4, RW},
	{"PYM_2_ROI1_U3",          0x06c8, RW},
	{"PYM_2_ROI0_U4",          0x06cc, RW},
	{"PYM_2_ROI1_U4",          0x06d0, RW},
	{"PYM_2_ROI0_U5",          0x06d4, RW},
	{"PYM_2_ROI1_U5",          0x06d8, RW},
	{"PYM_2_US_FACTOR_1",      0x06dc, RW},
	{"PYM_2_US_FACTOR_2",      0x06e0, RW},
	{"PYM_2_SRC_WIDTH_DS1",    0x06e4, RW},
	{"PYM_2_SRC_WIDTH_DS2",    0x06e8, RW},
	{"PYM_2_SRC_WIDTH_DS3",    0x06ec, RW},
	{"PYM_2_SRC_WIDTH_DS4",    0x06f0, RW},
	{"PYM_2_SRC_WIDTH_DS5",    0x06f4, RW},
	{"PYM_2_SRC_WIDTH_DS6",    0x06f8, RW},
	{"PYM_2_SRC_WIDTH_DS7",    0x06fc, RW},
	{"PYM_2_SRC_WIDTH_DS8",    0x0700, RW},
	{"PYM_2_SRC_WIDTH_DS9",    0x0704, RW},
	{"PYM_2_SRC_WIDTH_US1",    0x0708, RW},
	{"PYM_2_SRC_WIDTH_US2",    0x070c, RW},
	{"PYM_2_SRC_WIDTH_US3",    0x0710, RW},
	{"PYM_2_CONFIG_RDY",       0x0714, RW},

	{"PYM_3_PYRAMIDE_DS_CTRL", 0x0800, RW},
	{"PYM_3_PYRAMIDE_US_CTRL", 0x0804, RW},
	{"PYM_3_IMG_RES_SRC",      0x0808, RW},
	{"PYM_3_DS_FACTOR_1",      0x080c, RW},
	{"PYM_3_DS_FACTOR_2",      0x0810, RW},
	{"PYM_3_DS_FACTOR_3",      0x0814, RW},
	{"PYM_3_DS_FACTOR_4",      0x0818, RW},
	{"PYM_3_ROI0_P1",          0x081c, RW},
	{"PYM_3_ROI1_P1",          0x0820, RW},
	{"PYM_3_ROI0_P2",          0x0824, RW},
	{"PYM_3_ROI1_P2",          0x0828, RW},
	{"PYM_3_ROI0_P3",          0x082c, RW},
	{"PYM_3_ROI1_P3",          0x0830, RW},
	{"PYM_3_ROI0_P5",          0x0834, RW},
	{"PYM_3_ROI1_P5",          0x0838, RW},
	{"PYM_3_ROI0_P6",          0x083c, RW},
	{"PYM_3_ROI1_P6",          0x0840, RW},
	{"PYM_3_ROI0_P7",          0x0844, RW},
	{"PYM_3_ROI1_P7",          0x0848, RW},
	{"PYM_3_ROI0_P9",          0x084c, RW},
	{"PYM_3_ROI1_P9",          0x0850, RW},
	{"PYM_3_ROI0_P10",         0x0854, RW},
	{"PYM_3_ROI1_P10",         0x0858, RW},
	{"PYM_3_ROI0_P11",         0x085c, RW},
	{"PYM_3_ROI1_P11",         0x0860, RW},
	{"PYM_3_ROI0_P13",         0x0864, RW},
	{"PYM_3_ROI1_P13",         0x0868, RW},
	{"PYM_3_ROI0_P14",         0x086c, RW},
	{"PYM_3_ROI1_P14",         0x0870, RW},
	{"PYM_3_ROI0_P15",         0x0874, RW},
	{"PYM_3_ROI1_P15",         0x0878, RW},
	{"PYM_3_ROI0_P17",         0x087c, RW},
	{"PYM_3_ROI1_P17",         0x0880, RW},
	{"PYM_3_ROI0_P18",         0x0884, RW},
	{"PYM_3_ROI1_P18",         0x0888, RW},
	{"PYM_3_ROI0_P19",         0x088c, RW},
	{"PYM_3_ROI1_P19",         0x0890, RW},
	{"PYM_3_ROI0_P21",         0x0894, RW},
	{"PYM_3_ROI1_P21",         0x0898, RW},
	{"PYM_3_ROI0_P22",         0x089c, RW},
	{"PYM_3_ROI1_P22",         0x08a0, RW},
	{"PYM_3_ROI0_P23",         0x08a4, RW},
	{"PYM_3_ROI1_P23",         0x08a8, RW},
	{"PYM_3_ROI0_U0",          0x08ac, RW},
	{"PYM_3_ROI1_U0",          0x08b0, RW},
	{"PYM_3_ROI0_U1",          0x08b4, RW},
	{"PYM_3_ROI1_U1",          0x08b8, RW},
	{"PYM_3_ROI0_U2",          0x08bc, RW},
	{"PYM_3_ROI1_U2",          0x08c0, RW},
	{"PYM_3_ROI0_U3",          0x08c4, RW},
	{"PYM_3_ROI1_U3",          0x08c8, RW},
	{"PYM_3_ROI0_U4",          0x08cc, RW},
	{"PYM_3_ROI1_U4",          0x08d0, RW},
	{"PYM_3_ROI0_U5",          0x08d4, RW},
	{"PYM_3_ROI1_U5",          0x08d8, RW},
	{"PYM_3_US_FACTOR_1",      0x08dc, RW},
	{"PYM_3_US_FACTOR_2",      0x08e0, RW},
	{"PYM_3_SRC_WIDTH_DS1",    0x08e4, RW},
	{"PYM_3_SRC_WIDTH_DS2",    0x08e8, RW},
	{"PYM_3_SRC_WIDTH_DS3",    0x08ec, RW},
	{"PYM_3_SRC_WIDTH_DS4",    0x08f0, RW},
	{"PYM_3_SRC_WIDTH_DS5",    0x08f4, RW},
	{"PYM_3_SRC_WIDTH_DS6",    0x08f8, RW},
	{"PYM_3_SRC_WIDTH_DS7",    0x08fc, RW},
	{"PYM_3_SRC_WIDTH_DS8",    0x0900, RW},
	{"PYM_3_SRC_WIDTH_DS9",    0x0904, RW},
	{"PYM_3_SRC_WIDTH_US1",    0x0908, RW},
	{"PYM_3_SRC_WIDTH_US2",    0x090c, RW},
	{"PYM_3_SRC_WIDTH_US3",    0x0910, RW},
	{"PYM_3_CONFIG_RDY",       0x0914, RW},
};

enum pym_reg_field{
	PYM_F_DDRCLK_GATE_EN,
	PYM_F_IPUCLK_GATE_EN,
	PYM_F_SEL_IPU_MODE,
	PYM_F_IMG_SRC,
	PYM_F_ENABLE,
	PYM_F_IMG_Y_ADDR_DDR,
	PYM_F_IMG_C_ADDR_DDR,
	PYM_F_IMG_ADDR_Y,
	PYM_F_IMG_Y_ADDR_DDR_P1,
	PYM_F_IMG_Y_ADDR_DDR_P2,
	PYM_F_IMG_Y_ADDR_DDR_P3,
	PYM_F_IMG_Y_ADDR_DDR_P4,
	PYM_F_IMG_Y_ADDR_DDR_P5,
	PYM_F_IMG_Y_ADDR_DDR_P6,
	PYM_F_IMG_Y_ADDR_DDR_P7,
	PYM_F_IMG_Y_ADDR_DDR_P8,
	PYM_F_IMG_Y_ADDR_DDR_P9,
	PYM_F_IMG_Y_ADDR_DDR_P10,
	PYM_F_IMG_Y_ADDR_DDR_P11,
	PYM_F_IMG_Y_ADDR_DDR_P12,
	PYM_F_IMG_Y_ADDR_DDR_P13,
	PYM_F_IMG_Y_ADDR_DDR_P14,
	PYM_F_IMG_Y_ADDR_DDR_P15,
	PYM_F_IMG_Y_ADDR_DDR_P16,
	PYM_F_IMG_Y_ADDR_DDR_P17,
	PYM_F_IMG_Y_ADDR_DDR_P18,
	PYM_F_IMG_Y_ADDR_DDR_P19,
	PYM_F_IMG_Y_ADDR_DDR_P20,
	PYM_F_IMG_Y_ADDR_DDR_P21,
	PYM_F_IMG_Y_ADDR_DDR_P22,
	PYM_F_IMG_Y_ADDR_DDR_P23,
	PYM_F_IMG_ADDR_C,
	PYM_F_IMG_C_ADDR_DDR_P1,
	PYM_F_IMG_C_ADDR_DDR_P2,
	PYM_F_IMG_C_ADDR_DDR_P3,
	PYM_F_IMG_C_ADDR_DDR_P4,
	PYM_F_IMG_C_ADDR_DDR_P5,
	PYM_F_IMG_C_ADDR_DDR_P6,
	PYM_F_IMG_C_ADDR_DDR_P7,
	PYM_F_IMG_C_ADDR_DDR_P8,
	PYM_F_IMG_C_ADDR_DDR_P9,
	PYM_F_IMG_C_ADDR_DDR_P10,
	PYM_F_IMG_C_ADDR_DDR_P11,
	PYM_F_IMG_C_ADDR_DDR_P12,
	PYM_F_IMG_C_ADDR_DDR_P13,
	PYM_F_IMG_C_ADDR_DDR_P14,
	PYM_F_IMG_C_ADDR_DDR_P15,
	PYM_F_IMG_C_ADDR_DDR_P16,
	PYM_F_IMG_C_ADDR_DDR_P17,
	PYM_F_IMG_C_ADDR_DDR_P18,
	PYM_F_IMG_C_ADDR_DDR_P19,
	PYM_F_IMG_C_ADDR_DDR_P20,
	PYM_F_IMG_C_ADDR_DDR_P21,
	PYM_F_IMG_C_ADDR_DDR_P22,
	PYM_F_IMG_C_ADDR_DDR_P23,
	PYM_F_IMG_Y_ADDR_U0,
	PYM_F_IMG_Y_ADDR_U1,
	PYM_F_IMG_Y_ADDR_U2,
	PYM_F_IMG_Y_ADDR_U3,
	PYM_F_IMG_Y_ADDR_U4,
	PYM_F_IMG_Y_ADDR_U5,
	PYM_F_IMG_C_ADDR_U0,
	PYM_F_IMG_C_ADDR_U1,
	PYM_F_IMG_C_ADDR_U2,
	PYM_F_IMG_C_ADDR_U3,
	PYM_F_IMG_C_ADDR_U4,
	PYM_F_IMG_C_ADDR_U5,
	PYM_F_V_ERR,
	PYM_F_H_ERR,
	PYM_F_CFG,
	PYM_F_WD_MAXLEN_M0,
	PYM_F_WD_ENDIAN_M0,
	PYM_F_WD_PRIORITY_M0,
	PYM_F_WD_MAXLEN_M1,
	PYM_F_WD_ENDIAN_M1,
	PYM_F_WD_PRIORITY_M1,
	PYM_F_WD_MAXLEN_M2,
	PYM_F_WD_ENDIAN_M2,
	PYM_F_WD_PRIORITY_M2,
	PYM_F_WD_MAXLEN_M3,
	PYM_F_WD_ENDIAN_M3,
	PYM_F_WD_PRIORITY_M3,
	PYM_F_WD_MAXLEN_M4,
	PYM_F_WD_ENDIAN_M4,
	PYM_F_WD_PRIORITY_M4,
	PYM_F_WD_MAXLEN_M5,
	PYM_F_WD_ENDIAN_M5,
	PYM_F_WD_PRIORITY_M5,
	PYM_F_RD_MAXLEN_M0,
	PYM_F_RD_ENDIAN_M0,
	PYM_F_RD_PRIORITY_M0,
	PYM_F_RD_MAXLEN_M1,
	PYM_F_RD_ENDIAN_M1,
	PYM_F_RD_PRIORITY_M1,
	PYM_F_WR_LINE_UV,
	PYM_F_WR_LINE_Y,
	PYM_F_FRAME_ID,
	PYM_F_FRAME_START_EN,
	PYM_F_FRAME_DONE_EN,
	PYM_F_FRAME_DROP_US_EN,
	PYM_F_FRAME_DROP_DS_EN,
	PYM_F_FRAME_START,
	PYM_F_FRAME_DONE,
	PYM_F_FRAME_DROP_US,
	PYM_F_FRAME_DROP_DS,
	PYM_F_DDR_START,
	PYM_F_FRAME_ID_VALUE,
	PYM_F_CONFIG_ID,
	PYM_F_CONFIG_COMMON_RDY,

	PYM_F_DS_UV_BYPASS,
	PYM_F_DS_LAYER_EN,
	PYM_F_UV_CLK_GATE_EN,
	PYM_F_US_CLK_GATE_EN,
	PYM_F_US_UV_BYPASS,
	PYM_F_US_LAYER_EN,
	PYM_F_IMG_SRC_W,
	PYM_F_IMG_SRC_H,
	PYM_F_DS_FACTOR_P1,
	PYM_F_DS_FACTOR_P2,
	PYM_F_DS_FACTOR_P3,
	PYM_F_DS_FACTOR_P5,
	PYM_F_DS_FACTOR_P6,
	PYM_F_DS_FACTOR_P7,
	PYM_F_DS_FACTOR_P9,
	PYM_F_DS_FACTOR_P10,
	PYM_F_DS_FACTOR_P11,
	PYM_F_DS_FACTOR_P13,
	PYM_F_DS_FACTOR_P14,
	PYM_F_DS_FACTOR_P15,
	PYM_F_DS_FACTOR_P17,
	PYM_F_DS_FACTOR_P18,
	PYM_F_DS_FACTOR_P19,
	PYM_F_DS_FACTOR_P21,
	PYM_F_DS_FACTOR_P22,
	PYM_F_DS_FACTOR_P23,
	PYM_F_ROI_LEFT_P1,
	PYM_F_ROI_TOP_P1,
	PYM_F_ROI_WIDTH_P1,
	PYM_F_ROI_HEIGHT_P1,
	PYM_F_ROI_LEFT_P2,
	PYM_F_ROI_TOP_P2,
	PYM_F_ROI_WIDTH_P2,
	PYM_F_ROI_HEIGHT_P2,
	PYM_F_ROI_LEFT_P3,
	PYM_F_ROI_TOP_P3,
	PYM_F_ROI_WIDTH_P3,
	PYM_F_ROI_HEIGHT_P3,
	PYM_F_ROI_LEFT_P5,
	PYM_F_ROI_TOP_P5,
	PYM_F_ROI_WIDTH_P5,
	PYM_F_ROI_HEIGHT_P5,
	PYM_F_ROI_LEFT_P6,
	PYM_F_ROI_TOP_P6,
	PYM_F_ROI_WIDTH_P6,
	PYM_F_ROI_HEIGHT_P6,
	PYM_F_ROI_LEFT_P7,
	PYM_F_ROI_TOP_P7,
	PYM_F_ROI_WIDTH_P7,
	PYM_F_ROI_HEIGHT_P7,
	PYM_F_ROI_LEFT_P9,
	PYM_F_ROI_TOP_P9,
	PYM_F_ROI_WIDTH_P9,
	PYM_F_ROI_HEIGHT_P9,
	PYM_F_ROI_LEFT_P10,
	PYM_F_ROI_TOP_P10,
	PYM_F_ROI_WIDTH_P10,
	PYM_F_ROI_HEIGHT_P10,
	PYM_F_ROI_LEFT_P11,
	PYM_F_ROI_TOP_P11,
	PYM_F_ROI_WIDTH_P11,
	PYM_F_ROI_HEIGHT_P11,
	PYM_F_ROI_LEFT_P13,
	PYM_F_ROI_TOP_P13,
	PYM_F_ROI_WIDTH_P13,
	PYM_F_ROI_HEIGHT_P13,
	PYM_F_ROI_LEFT_P14,
	PYM_F_ROI_TOP_P14,
	PYM_F_ROI_WIDTH_P14,
	PYM_F_ROI_HEIGHT_P14,
	PYM_F_ROI_LEFT_P15,
	PYM_F_ROI_TOP_P15,
	PYM_F_ROI_WIDTH_P15,
	PYM_F_ROI_HEIGHT_P15,
	PYM_F_ROI_LEFT_P17,
	PYM_F_ROI_TOP_P17,
	PYM_F_ROI_WIDTH_P17,
	PYM_F_ROI_HEIGHT_P17,
	PYM_F_ROI_LEFT_P18,
	PYM_F_ROI_TOP_P18,
	PYM_F_ROI_WIDTH_P18,
	PYM_F_ROI_HEIGHT_P18,
	PYM_F_ROI_LEFT_P19,
	PYM_F_ROI_TOP_P19,
	PYM_F_ROI_WIDTH_P19,
	PYM_F_ROI_HEIGHT_P19,
	PYM_F_ROI_LEFT_P21,
	PYM_F_ROI_TOP_P21,
	PYM_F_ROI_WIDTH_P21,
	PYM_F_ROI_HEIGHT_P21,
	PYM_F_ROI_LEFT_P22,
	PYM_F_ROI_TOP_P22,
	PYM_F_ROI_WIDTH_P22,
	PYM_F_ROI_HEIGHT_P22,
	PYM_F_ROI_LEFT_P23,
	PYM_F_ROI_TOP_P23,
	PYM_F_ROI_WIDTH_P23,
	PYM_F_ROI_HEIGHT_P23,
	PYM_F_ROI_LEFT_U0,
	PYM_F_ROI_TOP_U0,
	PYM_F_ROI_WIDTH_U0,
	PYM_F_ROI_HEIGHT_U0,
	PYM_F_ROI_LEFT_U1,
	PYM_F_ROI_TOP_U1,
	PYM_F_ROI_WIDTH_U1,
	PYM_F_ROI_HEIGHT_U1,
	PYM_F_ROI_LEFT_U2,
	PYM_F_ROI_TOP_U2,
	PYM_F_ROI_WIDTH_U2,
	PYM_F_ROI_HEIGHT_U2,
	PYM_F_ROI_LEFT_U3,
	PYM_F_ROI_TOP_U3,
	PYM_F_ROI_WIDTH_U3,
	PYM_F_ROI_HEIGHT_U3,
	PYM_F_ROI_LEFT_U4,
	PYM_F_ROI_TOP_U4,
	PYM_F_ROI_WIDTH_U4,
	PYM_F_ROI_HEIGHT_U4,
	PYM_F_ROI_LEFT_U5,
	PYM_F_ROI_TOP_U5,
	PYM_F_ROI_WIDTH_U5,
	PYM_F_ROI_HEIGHT_U5,
	PYM_F_US_FACTOR_U0,
	PYM_F_US_FACTOR_U1,
	PYM_F_US_FACTOR_U2,
	PYM_F_US_FACTOR_U3,
	PYM_F_US_FACTOR_U4,
	PYM_F_US_FACTOR_U5,
	PYM_F_SRC_WIDTH_P2,
	PYM_F_SRC_WIDTH_P1,
	PYM_F_SRC_WIDTH_P5,
	PYM_F_SRC_WIDTH_P3,
	PYM_F_SRC_WIDTH_P7,
	PYM_F_SRC_WIDTH_P6,
	PYM_F_SRC_WIDTH_P10,
	PYM_F_SRC_WIDTH_P9,
	PYM_F_SRC_WIDTH_P13,
	PYM_F_SRC_WIDTH_P11,
	PYM_F_SRC_WIDTH_P15,
	PYM_F_SRC_WIDTH_P14,
	PYM_F_SRC_WIDTH_P18,
	PYM_F_SRC_WIDTH_P17,
	PYM_F_SRC_WIDTH_P21,
	PYM_F_SRC_WIDTH_P19,
	PYM_F_SRC_WIDTH_P23,
	PYM_F_SRC_WIDTH_P22,
	PYM_F_SRC_WIDTH_U1,
	PYM_F_SRC_WIDTH_U0,
	PYM_F_SRC_WIDTH_U3,
	PYM_F_SRC_WIDTH_U2,
	PYM_F_SRC_WIDTH_U5,
	PYM_F_SRC_WIDTH_U4,
	PYM_F_CONFIG_RDY,
	NUM_OF_PYM_FIELD,
};

static struct vio_field_def pym_fields[NUM_OF_PYM_FIELD] = {
	{PYM_PYRAMID_CTRL,	PYM_F_DDRCLK_GATE_EN, 29, 1 , 1},
	{PYM_PYRAMID_CTRL,	PYM_F_IPUCLK_GATE_EN, 28, 1 , 1},
	{PYM_PYRAMID_CTRL,	PYM_F_SEL_IPU_MODE,   3 , 1 , 0},
	{PYM_PYRAMID_CTRL,	PYM_F_IMG_SRC,		  1 , 1 , 0},
	{PYM_PYRAMID_CTRL,	PYM_F_ENABLE,		  0 , 1 , 0},
	{PYM_IMG_Y_ADDR_DDR,		PYM_F_IMG_Y_ADDR_DDR, 	  0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR,		PYM_F_IMG_C_ADDR_DDR, 	  0 , 32, 0},
	{PYM_IMG_ADDR_Y,			PYM_F_IMG_ADDR_Y,	  	  0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P1,		PYM_F_IMG_Y_ADDR_DDR_P1,  0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P2,		PYM_F_IMG_Y_ADDR_DDR_P2,  0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P3,		PYM_F_IMG_Y_ADDR_DDR_P3,  0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P4,		PYM_F_IMG_Y_ADDR_DDR_P4,  0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P5,		PYM_F_IMG_Y_ADDR_DDR_P5,  0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P6,		PYM_F_IMG_Y_ADDR_DDR_P6,  0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P7,		PYM_F_IMG_Y_ADDR_DDR_P7,  0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P8,		PYM_F_IMG_Y_ADDR_DDR_P8,  0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P9,		PYM_F_IMG_Y_ADDR_DDR_P9,  0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P10,	PYM_F_IMG_Y_ADDR_DDR_P10, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P11,	PYM_F_IMG_Y_ADDR_DDR_P11, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P12,	PYM_F_IMG_Y_ADDR_DDR_P12, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P13,	PYM_F_IMG_Y_ADDR_DDR_P13, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P14,	PYM_F_IMG_Y_ADDR_DDR_P14, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P15,	PYM_F_IMG_Y_ADDR_DDR_P15, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P16,	PYM_F_IMG_Y_ADDR_DDR_P16, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P17,	PYM_F_IMG_Y_ADDR_DDR_P17, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P18,	PYM_F_IMG_Y_ADDR_DDR_P18, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P19,	PYM_F_IMG_Y_ADDR_DDR_P19, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P20,	PYM_F_IMG_Y_ADDR_DDR_P20, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P21,	PYM_F_IMG_Y_ADDR_DDR_P21, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P22,	PYM_F_IMG_Y_ADDR_DDR_P22, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_DDR_P23,	PYM_F_IMG_Y_ADDR_DDR_P23, 0 , 32, 0},
	{PYM_IMG_ADDR_C,			PYM_F_IMG_ADDR_C,         0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P1,		PYM_F_IMG_C_ADDR_DDR_P1,  0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P2,		PYM_F_IMG_C_ADDR_DDR_P2,  0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P3,		PYM_F_IMG_C_ADDR_DDR_P3,  0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P4,		PYM_F_IMG_C_ADDR_DDR_P4,  0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P5,		PYM_F_IMG_C_ADDR_DDR_P5,  0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P6,		PYM_F_IMG_C_ADDR_DDR_P6,  0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P7,		PYM_F_IMG_C_ADDR_DDR_P7,  0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P8,		PYM_F_IMG_C_ADDR_DDR_P8,  0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P9,		PYM_F_IMG_C_ADDR_DDR_P9,  0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P10,	PYM_F_IMG_C_ADDR_DDR_P10, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P11,	PYM_F_IMG_C_ADDR_DDR_P11, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P12,	PYM_F_IMG_C_ADDR_DDR_P12, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P13,	PYM_F_IMG_C_ADDR_DDR_P13, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P14,	PYM_F_IMG_C_ADDR_DDR_P14, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P15,	PYM_F_IMG_C_ADDR_DDR_P15, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P16,	PYM_F_IMG_C_ADDR_DDR_P16, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P17,	PYM_F_IMG_C_ADDR_DDR_P17, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P18,	PYM_F_IMG_C_ADDR_DDR_P18, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P19,	PYM_F_IMG_C_ADDR_DDR_P19, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P20,	PYM_F_IMG_C_ADDR_DDR_P20, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P21,	PYM_F_IMG_C_ADDR_DDR_P21, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P22,	PYM_F_IMG_C_ADDR_DDR_P22, 0 , 32, 0},
	{PYM_IMG_C_ADDR_DDR_P23,	PYM_F_IMG_C_ADDR_DDR_P23, 0 , 32, 0},
	{PYM_IMG_Y_ADDR_U0,			PYM_F_IMG_Y_ADDR_U0,      0 , 32, 0},
	{PYM_IMG_Y_ADDR_U1,			PYM_F_IMG_Y_ADDR_U1,      0 , 32, 0},
	{PYM_IMG_Y_ADDR_U2,			PYM_F_IMG_Y_ADDR_U2,      0 , 32, 0},
	{PYM_IMG_Y_ADDR_U3,			PYM_F_IMG_Y_ADDR_U3,      0 , 32, 0},
	{PYM_IMG_Y_ADDR_U4,			PYM_F_IMG_Y_ADDR_U4,      0 , 32, 0},
	{PYM_IMG_Y_ADDR_U5,			PYM_F_IMG_Y_ADDR_U5,      0 , 32, 0},
	{PYM_IMG_C_ADDR_U0,			PYM_F_IMG_C_ADDR_U0,      0 , 32, 0},
	{PYM_IMG_C_ADDR_U1,			PYM_F_IMG_C_ADDR_U1,      0 , 32, 0},
	{PYM_IMG_C_ADDR_U2,			PYM_F_IMG_C_ADDR_U2,      0 , 32, 0},
	{PYM_IMG_C_ADDR_U3,			PYM_F_IMG_C_ADDR_U3,      0 , 32, 0},
	{PYM_IMG_C_ADDR_U4,			PYM_F_IMG_C_ADDR_U4,      0 , 32, 0},
	{PYM_IMG_C_ADDR_U5,			PYM_F_IMG_C_ADDR_U5,      0 , 32, 0},
	{PYM_ERR_CNT,	PYM_F_V_ERR,	16, 16, 0},
	{PYM_ERR_CNT,	PYM_F_H_ERR,	0 , 16, 0},
	{PYM_CFG,		PYM_F_CFG,		0 , 4 , 0},
	{PYM_CTRL_WM_0,		PYM_F_WD_MAXLEN_M0,		8 , 8 , 0},
	{PYM_CTRL_WM_0,		PYM_F_WD_ENDIAN_M0,		4 , 4 , 0},
	{PYM_CTRL_WM_0,		PYM_F_WD_PRIORITY_M0,	0 , 4 , 0},
	{PYM_CTRL_WM_1,		PYM_F_WD_MAXLEN_M1,     8 , 8 , 0},
	{PYM_CTRL_WM_1,		PYM_F_WD_ENDIAN_M1,     4 , 4 , 0},
	{PYM_CTRL_WM_1,		PYM_F_WD_PRIORITY_M1,   0 , 4 , 0},
	{PYM_CTRL_WM_2,		PYM_F_WD_MAXLEN_M2,     8 , 8 , 0},
	{PYM_CTRL_WM_2,		PYM_F_WD_ENDIAN_M2,     4 , 4 , 0},
	{PYM_CTRL_WM_2,		PYM_F_WD_PRIORITY_M2,   0 , 4 , 0},
	{PYM_CTRL_WM_3,		PYM_F_WD_MAXLEN_M3,     8 , 8 , 0},
	{PYM_CTRL_WM_3,		PYM_F_WD_ENDIAN_M3,     4 , 4 , 0},
	{PYM_CTRL_WM_3,		PYM_F_WD_PRIORITY_M3,   0 , 4 , 0},
	{PYM_CTRL_WM_4,		PYM_F_WD_MAXLEN_M4,     8 , 8 , 0},
	{PYM_CTRL_WM_4,		PYM_F_WD_ENDIAN_M4,     4 , 4 , 0},
	{PYM_CTRL_WM_4,		PYM_F_WD_PRIORITY_M4,   0 , 4 , 0},
	{PYM_CTRL_WM_5,		PYM_F_WD_MAXLEN_M5,     8 , 8 , 0},
	{PYM_CTRL_WM_5,		PYM_F_WD_ENDIAN_M5,     4 , 4 , 0},
	{PYM_CTRL_WM_5,		PYM_F_WD_PRIORITY_M5,   0 , 4 , 0},
	{PYM_CTRL_RM_0,		PYM_F_RD_MAXLEN_M0,     8 , 8 , 0},
	{PYM_CTRL_RM_0,		PYM_F_RD_ENDIAN_M0,     4 , 4 , 0},
	{PYM_CTRL_RM_0,		PYM_F_RD_PRIORITY_M0,   0 , 4 , 0},
	{PYM_CTRL_RM_1,		PYM_F_RD_MAXLEN_M1,     8 , 8 , 0},
	{PYM_CTRL_RM_1,		PYM_F_RD_ENDIAN_M1,     4 , 4 , 0},
	{PYM_CTRL_RM_1,		PYM_F_RD_PRIORITY_M1,   0 , 4 , 0},
	{PYM_WR_LINE,		PYM_F_WR_LINE_UV,       16, 13, 0},
	{PYM_WR_LINE,		PYM_F_WR_LINE_Y,        0 , 12, 0},
	{PYM_FRAME_ID,		PYM_F_FRAME_ID,         0 , 15, 0},
	{PYM_INT_MASK,		PYM_F_FRAME_START_EN,    3 , 1 , 0},
	{PYM_INT_MASK,		PYM_F_FRAME_DONE_EN,     2 , 1 , 0},
	{PYM_INT_MASK,		PYM_F_FRAME_DROP_US_EN,  1 , 1 , 0},
	{PYM_INT_MASK,		PYM_F_FRAME_DROP_DS_EN,  0 , 1 , 0},
	{PYM_INT_STATUS,	PYM_F_FRAME_START,       3 , 1 , 0},
	{PYM_INT_STATUS,	PYM_F_FRAME_DONE,        2 , 1 , 0},
	{PYM_INT_STATUS,	PYM_F_FRAME_DROP_US,     1 , 1 , 0},
	{PYM_INT_STATUS,	PYM_F_FRAME_DROP_DS,     0 , 1 , 0},
	{PYM_DDR_START,		PYM_F_DDR_START,         0 , 1 , 0},
	{PYM_FRAME_ID_VALUE,	PYM_F_FRAME_ID_VALUE,  0 , 16, 0},
	{PYM_CONFIG_ID,			PYM_F_CONFIG_ID,       0 , 2 , 0},
	{PYM_CONFIG_RDY,		PYM_F_CONFIG_COMMON_RDY,      0 , 1 , 0},

	{PYM_0_PYRAMIDE_DS_CTRL,	PYM_F_DS_UV_BYPASS,    8 , 18, 0},
	{PYM_0_PYRAMIDE_DS_CTRL,	PYM_F_DS_LAYER_EN,     0 , 5 , 0},
	{PYM_0_PYRAMIDE_US_CTRL,	PYM_F_UV_CLK_GATE_EN,  17, 1 , 1},
	{PYM_0_PYRAMIDE_US_CTRL,	PYM_F_US_CLK_GATE_EN,  16, 1 , 1},
	{PYM_0_PYRAMIDE_US_CTRL,	PYM_F_US_UV_BYPASS,    8 , 6 , 0},
	{PYM_0_PYRAMIDE_US_CTRL,	PYM_F_US_LAYER_EN,     0 , 6 , 0},
	{PYM_0_IMG_RES_SRC,			PYM_F_IMG_SRC_W,       16, 13, 0},
	{PYM_0_IMG_RES_SRC,			PYM_F_IMG_SRC_H,       0 , 13, 0},
	{PYM_0_DS_FACTOR_1,		PYM_F_DS_FACTOR_P1,     24, 6 , 0},
	{PYM_0_DS_FACTOR_1,		PYM_F_DS_FACTOR_P2,     18, 6 , 0},
	{PYM_0_DS_FACTOR_1,		PYM_F_DS_FACTOR_P3,     12, 6 , 0},
	{PYM_0_DS_FACTOR_1,		PYM_F_DS_FACTOR_P5,     6 , 6 , 0},
	{PYM_0_DS_FACTOR_1,		PYM_F_DS_FACTOR_P6,     0 , 6 , 0},
	{PYM_0_DS_FACTOR_2,		PYM_F_DS_FACTOR_P7,     24, 6 , 0},
	{PYM_0_DS_FACTOR_2,		PYM_F_DS_FACTOR_P9,     18, 6 , 0},
	{PYM_0_DS_FACTOR_2,		PYM_F_DS_FACTOR_P10,    12, 6 , 0},
	{PYM_0_DS_FACTOR_2,		PYM_F_DS_FACTOR_P11,    6 , 6 , 0},
	{PYM_0_DS_FACTOR_2,		PYM_F_DS_FACTOR_P13,    0 , 6 , 0},
	{PYM_0_DS_FACTOR_3,		PYM_F_DS_FACTOR_P14,    24, 6 , 0},
	{PYM_0_DS_FACTOR_3,		PYM_F_DS_FACTOR_P15,    18, 6 , 0},
	{PYM_0_DS_FACTOR_3,		PYM_F_DS_FACTOR_P17,    12, 6 , 0},
	{PYM_0_DS_FACTOR_3,		PYM_F_DS_FACTOR_P18,    6 , 6 , 0},
	{PYM_0_DS_FACTOR_3,		PYM_F_DS_FACTOR_P19,    0 , 6 , 0},
	{PYM_0_DS_FACTOR_4,		PYM_F_DS_FACTOR_P21,    12, 6 , 0},
	{PYM_0_DS_FACTOR_4,		PYM_F_DS_FACTOR_P22,    6 , 6 , 0},
	{PYM_0_DS_FACTOR_4,		PYM_F_DS_FACTOR_P23,    0 , 6 , 0},
	{PYM_0_ROI0_P1,		PYM_F_ROI_LEFT_P1,     16, 12, 0},
	{PYM_0_ROI0_P1,		PYM_F_ROI_TOP_P1,      0 , 12, 0},
	{PYM_0_ROI1_P1,		PYM_F_ROI_WIDTH_P1,    16, 13, 0},
	{PYM_0_ROI1_P1,		PYM_F_ROI_HEIGHT_P1,   0 , 13, 0},
	{PYM_0_ROI0_P2,		PYM_F_ROI_LEFT_P2,     16, 12, 0},
	{PYM_0_ROI0_P2,		PYM_F_ROI_TOP_P2,      0 , 12, 0},
	{PYM_0_ROI1_P2,		PYM_F_ROI_WIDTH_P2,    16, 13, 0},
	{PYM_0_ROI1_P2,		PYM_F_ROI_HEIGHT_P2,   0 , 13, 0},
	{PYM_0_ROI0_P3,		PYM_F_ROI_LEFT_P3,     16, 12, 0},
	{PYM_0_ROI0_P3,		PYM_F_ROI_TOP_P3,      0 , 12, 0},
	{PYM_0_ROI1_P3,		PYM_F_ROI_WIDTH_P3,    16, 13, 0},
	{PYM_0_ROI1_P3,		PYM_F_ROI_HEIGHT_P3,   0 , 13, 0},
	{PYM_0_ROI0_P5,		PYM_F_ROI_LEFT_P5,     16, 12, 0},
	{PYM_0_ROI0_P5,		PYM_F_ROI_TOP_P5,      0 , 12, 0},
	{PYM_0_ROI1_P5,		PYM_F_ROI_WIDTH_P5,    16, 13, 0},
	{PYM_0_ROI1_P5,		PYM_F_ROI_HEIGHT_P5,   0 , 13, 0},
	{PYM_0_ROI0_P6,		PYM_F_ROI_LEFT_P6,     16, 12, 0},
	{PYM_0_ROI0_P6,		PYM_F_ROI_TOP_P6,      0 , 12, 0},
	{PYM_0_ROI1_P6,		PYM_F_ROI_WIDTH_P6,    16, 13, 0},
	{PYM_0_ROI1_P6,		PYM_F_ROI_HEIGHT_P6,   0 , 13, 0},
	{PYM_0_ROI0_P7,		PYM_F_ROI_LEFT_P7,     16, 12, 0},
	{PYM_0_ROI0_P7,		PYM_F_ROI_TOP_P7,      0 , 12, 0},
	{PYM_0_ROI1_P7,		PYM_F_ROI_WIDTH_P7,    16, 13, 0},
	{PYM_0_ROI1_P7,		PYM_F_ROI_HEIGHT_P7,   0 , 13, 0},
	{PYM_0_ROI0_P9,		PYM_F_ROI_LEFT_P9,     16, 12, 0},
	{PYM_0_ROI0_P9,		PYM_F_ROI_TOP_P9,      0 , 12, 0},
	{PYM_0_ROI1_P9,		PYM_F_ROI_WIDTH_P9,    16, 13, 0},
	{PYM_0_ROI1_P9,		PYM_F_ROI_HEIGHT_P9,   0 , 13, 0},
	{PYM_0_ROI0_P10,	PYM_F_ROI_LEFT_P10,    16, 12, 0},
	{PYM_0_ROI0_P10,	PYM_F_ROI_TOP_P10,     0 , 12, 0},
	{PYM_0_ROI1_P10,	PYM_F_ROI_WIDTH_P10,   16, 13, 0},
	{PYM_0_ROI1_P10,	PYM_F_ROI_HEIGHT_P10,  0 , 13, 0},
	{PYM_0_ROI0_P11,	PYM_F_ROI_LEFT_P11,    16, 12, 0},
	{PYM_0_ROI0_P11,	PYM_F_ROI_TOP_P11,     0 , 12, 0},
	{PYM_0_ROI1_P11,	PYM_F_ROI_WIDTH_P11,   16, 13, 0},
	{PYM_0_ROI1_P11,	PYM_F_ROI_HEIGHT_P11,  0 , 13, 0},
	{PYM_0_ROI0_P13,	PYM_F_ROI_LEFT_P13,    16, 12, 0},
	{PYM_0_ROI0_P13,	PYM_F_ROI_TOP_P13,     0 , 12, 0},
	{PYM_0_ROI1_P13,	PYM_F_ROI_WIDTH_P13,   16, 13, 0},
	{PYM_0_ROI1_P13,	PYM_F_ROI_HEIGHT_P13,  0 , 13, 0},
	{PYM_0_ROI0_P14,	PYM_F_ROI_LEFT_P14,    16, 12, 0},
	{PYM_0_ROI0_P14,	PYM_F_ROI_TOP_P14,     0 , 12, 0},
	{PYM_0_ROI1_P14,	PYM_F_ROI_WIDTH_P14,   16, 13, 0},
	{PYM_0_ROI1_P14,	PYM_F_ROI_HEIGHT_P14,  0 , 13, 0},
	{PYM_0_ROI0_P15,	PYM_F_ROI_LEFT_P15,    16, 12, 0},
	{PYM_0_ROI0_P15,	PYM_F_ROI_TOP_P15,     0 , 12, 0},
	{PYM_0_ROI1_P15,	PYM_F_ROI_WIDTH_P15,   16, 13, 0},
	{PYM_0_ROI1_P15,	PYM_F_ROI_HEIGHT_P15,  0 , 13, 0},
	{PYM_0_ROI0_P17,	PYM_F_ROI_LEFT_P17,    16, 12, 0},
	{PYM_0_ROI0_P17,	PYM_F_ROI_TOP_P17,     0 , 12, 0},
	{PYM_0_ROI1_P17,	PYM_F_ROI_WIDTH_P17,   16, 13, 0},
	{PYM_0_ROI1_P17,	PYM_F_ROI_HEIGHT_P17,  0 , 13, 0},
	{PYM_0_ROI0_P18,	PYM_F_ROI_LEFT_P18,    16, 12, 0},
	{PYM_0_ROI0_P18,	PYM_F_ROI_TOP_P18,     0 , 12, 0},
	{PYM_0_ROI1_P18,	PYM_F_ROI_WIDTH_P18,   16, 13, 0},
	{PYM_0_ROI1_P18,	PYM_F_ROI_HEIGHT_P18,  0 , 13, 0},
	{PYM_0_ROI0_P19,	PYM_F_ROI_LEFT_P19,    16, 12, 0},
	{PYM_0_ROI0_P19,	PYM_F_ROI_TOP_P19,     0 , 12, 0},
	{PYM_0_ROI1_P19,	PYM_F_ROI_WIDTH_P19,   16, 13, 0},
	{PYM_0_ROI1_P19,	PYM_F_ROI_HEIGHT_P19,  0 , 13, 0},
	{PYM_0_ROI0_P21,	PYM_F_ROI_LEFT_P21,    16, 12, 0},
	{PYM_0_ROI0_P21,	PYM_F_ROI_TOP_P21,     0 , 12, 0},
	{PYM_0_ROI1_P21,	PYM_F_ROI_WIDTH_P21,   16, 13, 0},
	{PYM_0_ROI1_P21,	PYM_F_ROI_HEIGHT_P21,  0 , 13, 0},
	{PYM_0_ROI0_P22,	PYM_F_ROI_LEFT_P22,    16, 12, 0},
	{PYM_0_ROI0_P22,	PYM_F_ROI_TOP_P22,     0 , 12, 0},
	{PYM_0_ROI1_P22,	PYM_F_ROI_WIDTH_P22,   16, 13, 0},
	{PYM_0_ROI1_P22,	PYM_F_ROI_HEIGHT_P22,  0 , 13, 0},
	{PYM_0_ROI0_P23,	PYM_F_ROI_LEFT_P23,    16, 12, 0},
	{PYM_0_ROI0_P23,	PYM_F_ROI_TOP_P23,     0 , 12, 0},
	{PYM_0_ROI1_P23,	PYM_F_ROI_WIDTH_P23,   16, 13, 0},
	{PYM_0_ROI1_P23,	PYM_F_ROI_HEIGHT_P23,  0 , 13, 0},
	{PYM_0_ROI0_U0,		PYM_F_ROI_LEFT_U0,     16, 12, 0},
	{PYM_0_ROI0_U0,		PYM_F_ROI_TOP_U0,      0 , 12, 0},
	{PYM_0_ROI1_U0,		PYM_F_ROI_WIDTH_U0,    16, 13, 0},
	{PYM_0_ROI1_U0,		PYM_F_ROI_HEIGHT_U0,   0 , 13, 0},
	{PYM_0_ROI0_U1,		PYM_F_ROI_LEFT_U1,     16, 12, 0},
	{PYM_0_ROI0_U1,		PYM_F_ROI_TOP_U1,      0 , 12, 0},
	{PYM_0_ROI1_U1,		PYM_F_ROI_WIDTH_U1,    16, 13, 0},
	{PYM_0_ROI1_U1,		PYM_F_ROI_HEIGHT_U1,   0 , 13, 0},
	{PYM_0_ROI0_U2,		PYM_F_ROI_LEFT_U2,     16, 12, 0},
	{PYM_0_ROI0_U2,		PYM_F_ROI_TOP_U2,      0 , 12, 0},
	{PYM_0_ROI1_U2,		PYM_F_ROI_WIDTH_U2,    16, 13, 0},
	{PYM_0_ROI1_U2,		PYM_F_ROI_HEIGHT_U2,   0 , 13, 0},
	{PYM_0_ROI0_U3,		PYM_F_ROI_LEFT_U3,     16, 12, 0},
	{PYM_0_ROI0_U3,		PYM_F_ROI_TOP_U3,      0 , 12, 0},
	{PYM_0_ROI1_U3,		PYM_F_ROI_WIDTH_U3,    16, 13, 0},
	{PYM_0_ROI1_U3,		PYM_F_ROI_HEIGHT_U3,   0 , 13, 0},
	{PYM_0_ROI0_U4,		PYM_F_ROI_LEFT_U4,     16, 12, 0},
	{PYM_0_ROI0_U4,		PYM_F_ROI_TOP_U4,      0 , 12, 0},
	{PYM_0_ROI1_U4,		PYM_F_ROI_WIDTH_U4,    16, 13, 0},
	{PYM_0_ROI1_U4,		PYM_F_ROI_HEIGHT_U4,   0 , 13, 0},
	{PYM_0_ROI0_U5,		PYM_F_ROI_LEFT_U5,     16, 12, 0},
	{PYM_0_ROI0_U5,		PYM_F_ROI_TOP_U5,      0 , 12, 0},
	{PYM_0_ROI1_U5,		PYM_F_ROI_WIDTH_U5,    16, 13, 0},
	{PYM_0_ROI1_U5,		PYM_F_ROI_HEIGHT_U5,   0 , 13, 0},
	{PYM_0_US_FACTOR_1,		PYM_F_US_FACTOR_U0,   24, 6 , 32},
	{PYM_0_US_FACTOR_1,		PYM_F_US_FACTOR_U1,   16, 6 , 28},
	{PYM_0_US_FACTOR_1,		PYM_F_US_FACTOR_U2,   8 , 6 , 20},
	{PYM_0_US_FACTOR_1,		PYM_F_US_FACTOR_U3,   0 , 6 , 19},
	{PYM_0_US_FACTOR_2,		PYM_F_US_FACTOR_U4,   8 , 6 , 14},
	{PYM_0_US_FACTOR_2,		PYM_F_US_FACTOR_U5,   0 , 6 , 10},
	{PYM_0_SRC_WIDTH_DS1,	PYM_F_SRC_WIDTH_P2,   16 , 13, 0},
	{PYM_0_SRC_WIDTH_DS1,	PYM_F_SRC_WIDTH_P1,   0 , 13, 0},
	{PYM_0_SRC_WIDTH_DS2,	PYM_F_SRC_WIDTH_P5,   16, 13, 0},
	{PYM_0_SRC_WIDTH_DS2,	PYM_F_SRC_WIDTH_P3,   0 , 13, 0},
	{PYM_0_SRC_WIDTH_DS3,	PYM_F_SRC_WIDTH_P7,   16, 13, 0},
	{PYM_0_SRC_WIDTH_DS3,	PYM_F_SRC_WIDTH_P6,   0 , 13, 0},
	{PYM_0_SRC_WIDTH_DS4,	PYM_F_SRC_WIDTH_P10,  16, 13, 0},
	{PYM_0_SRC_WIDTH_DS4,	PYM_F_SRC_WIDTH_P9,   0 , 13, 0},
	{PYM_0_SRC_WIDTH_DS5,	PYM_F_SRC_WIDTH_P13,  16, 13, 0},
	{PYM_0_SRC_WIDTH_DS5,	PYM_F_SRC_WIDTH_P11,  0 , 13, 0},
	{PYM_0_SRC_WIDTH_DS6,	PYM_F_SRC_WIDTH_P15,  16, 13, 0},
	{PYM_0_SRC_WIDTH_DS6,	PYM_F_SRC_WIDTH_P14,  0 , 13, 0},
	{PYM_0_SRC_WIDTH_DS7,	PYM_F_SRC_WIDTH_P18,  16, 13, 0},
	{PYM_0_SRC_WIDTH_DS7,	PYM_F_SRC_WIDTH_P17,  0 , 13, 0},
	{PYM_0_SRC_WIDTH_DS8,	PYM_F_SRC_WIDTH_P21,  16, 13, 0},
	{PYM_0_SRC_WIDTH_DS8,	PYM_F_SRC_WIDTH_P19,  0 , 13, 0},
	{PYM_0_SRC_WIDTH_DS9,	PYM_F_SRC_WIDTH_P23,  16, 13, 0},
	{PYM_0_SRC_WIDTH_DS9,	PYM_F_SRC_WIDTH_P22,  0 , 13, 0},
	{PYM_0_SRC_WIDTH_US1,	PYM_F_SRC_WIDTH_U1,   16, 13, 0},
	{PYM_0_SRC_WIDTH_US1,	PYM_F_SRC_WIDTH_U0,   0 , 13, 0},
	{PYM_0_SRC_WIDTH_US2,	PYM_F_SRC_WIDTH_U3,   16, 13, 0},
	{PYM_0_SRC_WIDTH_US2,	PYM_F_SRC_WIDTH_U2,   0 , 13, 0},
	{PYM_0_SRC_WIDTH_US3,	PYM_F_SRC_WIDTH_U5,   16, 13, 0},
	{PYM_0_SRC_WIDTH_US3,	PYM_F_SRC_WIDTH_U4,   0 , 13, 0},
	{PYM_0_CONFIG_RDY,		PYM_F_CONFIG_RDY,     0 , 1 , 0},
};

#endif
